#ifndef F28004X_PGA_H
#define F28004X_PGA_H

#ifdef __cplusplus
extern "C" {
#endif
//---------------------------------------------------------------------------
// PGA Individual Register Bit Definitions:

struct PGACTL1_BITS
{                       // bits description
    Uint32 PGAEN  : 1;  // 0 PGA Enable
    Uint32 RSEL   : 3;  // 3:1 Feed bank R select signal
    Uint32 PM     : 2;  // 5:4 PGA gain setting
    Uint32 GSEL   : 2;  // 7:6 INR input MUX select signal
    Uint32 PSEL   : 2;  // 9:8 INR input MUX select signal
    Uint32 SH4    : 1;  // 10  S4 Turn on signal.
    Uint32 SH3    : 1;  // 11  S3 Turn on signal.
    Uint32 rsvd1  : 1;  // 12 Reserved
    Uint32 SH1    : 1;  // 13 S1 Turn on signal.
    Uint32 ADJ_RF : 4;  // 17:14 RFILT Adjustment signal
    Uint32 rsvd2  : 14; // 31:18 Reserved
};

union PGACTL1_REG
{
    Uint32 all;
    struct PGACTL1_BITS bit;
};

struct PGALOCK1_BITS
{                      // bits description
    Uint32 PGACTL : 1; // 0 Lock bit for PGACTL.
};

union PGALOCK1_REG
{
    Uint32 all;
    struct PGALOCK1_BITS bit;
};

struct PGATYPE_BITS
{                    // bits description
    Uint32 REV  : 8; // 7:0 PGA Revision Field
    Uint32 TYPE : 8; // 15:8 PGA Type Field
};

union PGATYPE_REG
{
    Uint32 all;
    struct PGATYPE_BITS bit;
};

struct PGA1_REGS
{
    union PGACTL1_REG PGACTL;   // PGA Control Register
    union PGALOCK1_REG PGALOCK; // PGA Lock Register
    Uint32 rsvd[5];             // Reserved
    union PGATYPE_REG PGATYPE;  // PGA Type Register
};

//---------------------------------------------------------------------------

struct PGACTL2_BITS
{                      // bits description
    Uint32 PGAEN  : 1; // 0 PGA Enable
    Uint32 ADJ_RF : 4; // 4:1 RFILT Adjustment signal
    Uint32 RSEL   : 3; // 7:5 Feed bank R select signal
    Uint32 TRIM   : 1; // 8 PGA TRIM
    Uint32 CLA    : 1; // 9 PGA CLA
    Uint32 SH4    : 1; // 10 PGA S4 Turn on signal
};

union PGACTL2_REG
{
    Uint32 all;
    struct PGACTL2_BITS bit;
};

struct PGALOCK2_BITS
{                             // bits description
    Uint32 PGACTL        : 1; // 0 Lock bit for PGACTL.
    Uint32 PGAGAIN3TRIM  : 1; // 1 Lock bit for PGAGAIN3TRIM.
    Uint32 PGAGAIN6TRIM  : 1; // 2 Lock bit for PGAGAIN6TRIM.
    Uint32 PGAGAIN12TRIM : 1; // 3 Lock bit for PGAGAIN12TRIM.
    Uint32 PGAGAIN24TRIM : 1; // 4 Lock bit for PGAGAIN24TRIM.
    Uint32 PGAGAIN48TRIM : 1; // 5 Lock bit for PGAGAIN24TRIM.
};

union PGALOCK2_REG
{
    Uint32 all;
    struct PGALOCK2_BITS bit;
};

struct PGAGAINTRIM_BITS
{                          // bits description
    Uint32 GAINTRIM   : 8; // 7:0 Gain TRIM value, when gain setting is 3
    Uint32 OFFSETTRIM : 8; // 15:8 OFFSET TRIM value, when Gain setting is 3
};

union PGAGAINTRIM_REG
{
    Uint32 all;
    struct PGAGAINTRIM_BITS bit;
};

struct PGA2_REGS
{
    union PGACTL2_REG PGACTL;            // PGA Control Register
    union PGALOCK2_REG PGALOCK;          // PGA Lock Register
    union PGAGAINTRIM_REG PGAGAIN3TRIM;  // PGA Gain Trim Register for a gain setting of 3
    union PGAGAINTRIM_REG PGAGAIN6TRIM;  // PGA Gain Trim Register for a gain setting of 6
    union PGAGAINTRIM_REG PGAGAIN12TRIM; // PGA Gain Trim Register for a gain setting of 12
    union PGAGAINTRIM_REG PGAGAIN24TRIM; // PGA Gain Trim Register for a gain setting of 24
    union PGAGAINTRIM_REG PGAGAIN48TRIM; // PGA Gain Trim Register for a gain setting of 48
    union PGATYPE_REG PGATYPE;           // PGA Type Register
};

//---------------------------------------------------------------------------
// PGA External References & Function Declarations:
//

extern volatile struct PGA1_REGS Pga1Regs;
extern volatile struct PGA1_REGS Pga2Regs;
extern volatile struct PGA1_REGS Pga3Regs;

extern volatile struct PGA2_REGS Pga4Regs;
extern volatile struct PGA2_REGS Pga5Regs;
extern volatile struct PGA2_REGS Pga6Regs;
extern volatile struct PGA2_REGS Pga7Regs;

#ifdef __cplusplus
}
#endif /* extern "C" */

#endif
